1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to a memory testing apparatus which is formed as an integral part of an integrated circuit chip.
2. Description of the Related Art
The increased size and complexity of modern microelectronic integrated circuit chip design not only allows, but requires that more memory be moved on-chip.
This presents a difficult problem. The high-density nature of current RAM and ROM designs makes on-chip memories more susceptible to process and manufacturing flaws. They also tend to have much lower fault coverage than other logic during a given test program.
Even sophisticated Automatic Test Program Generator (ATPG) such as Sunrise, etc., which take advantage of a memory to test the logic in its shadow, do not actually generate vectors to test the memories themselves. Testing a memory in its shadow involves applying test data to memories through the logical circuitry of the chip. If the test results indicate a malfunction, it cannot be determined if the malfunction is in the logic circuitry or in the memory.
Functional test vectors extracted from a reference model performing some real-world operation constitute a good starting point. However, from the memory's perspective, the test is random, haphazard, and with poor controllability and observability. The advantage of functional and ATPG vectors is that it requires little effort on the part of Design Engineering and absolutely no hardware.
Specialized test vectors generated by sophisticated ATPG can easily increase fault coverage for an entire chip to the 95% level, with added scan registers.
However, these fault coverage numbers do not include the on-chip memories at all. Even though such tools may take advantage of a memory to test circuitry in its shadow, they do not actually target the memories at all.
There is more to testing a RAM than simply writing and reading each location. Specific patterns like "walking one's", "walking zero's", and "checkerboard" are required for thorough testing.
Built-In Self Test (BIST) circuitry automatically generates such patterns, and provides an output indicating whether the memory failed or passed the generated tests. The advantage over test vectors is that with BIST, the memories can be tested at any time in the field, and so offer some degree of continued fault detection.
However, the overhead is high, as BIST circuits tend to be quite large compared to the memory they test, especially for small memories. Also, the single Pass/Fail output does not provide desired information about the problem that Test Engineering might require.
There exists in the art a need for a memory testing apparatus which requires no extra pins, allows any memory to be written and read in any way desired in the field as well as on the tester, uses little added hardware, can be integrated easily with the existing "no-test-H/W" design, and has little impact on routing.